The present invention generally relates to an elastic store memory circuit, and more particularly to an elastic store memory circuit which generates a signal indicative of the type of data slip which takes place during read operation.
In the field of communications, there is a trend to process signals in digital form. For example, analog signals such as voice signals are converted into digital signals. In order to transmit digital signals, digital signals are multiplexed and/or converted into transmission signals having bit rates different from those of the digital signals. The transmission signals thus obtained are sent to receive devices through transmission paths. On the receive side, transmission signals are demultiplexed and/or converted to digital signals having the original bit rates.
Conventionally, an elastic store memory is used for realizing a multiplexing/demultiplexing procedure or a bit rate conversion procedure. As is well known, an elastic store memory executes the write operation and read operation simultaneously and asynchronously. Input data is written into the elastic store memory at the bit rate of the input data, while data is read out therefrom at a desired bit rate.
Referring to FIG. 1, there is shown a transmission system, which includes a plurality of data transmission terminals (DT) 31, a data terminal controller (DTC) 32 and a network (NW) 33. The data transmission terminals 31 are respectively provided with a plurality of transmission lines 30. Each of the data transmission terminals 31 asynchronously receives a data signal (such as a digitized voice signal or an information signal) in a predetermined frame format, and converts the same into a synchronized signal. The data terminal controller 32 receives the synchronized signals output by the data transmission terminals 31 and multiplexes the same to thereby generate a transmission signal. The network 33 receives the transmission signal produced and output by the data terminal controller 32, and sends the same to the data terminal controller 32 by a switching procedure. The data terminal controller 32 carries out a procedure for demultiplexing the received transmission signal, and sends demultiplexed signals to the data transmission terminals 31.
Each of the data transmission terminals 31 converts the asynchronous input data signal into the digitized signal which is in synchronism with a synchronizing signal having a bit rate suitable for multiplexing. For this purpose, each of the data transmission terminals 31 is provided with an elastic store memory in which the write operation is performed separately from the read operation.
FIG. 2 is a diagram illustrating a conventional elastic store memory. The elastic store memory shown in FIG. 2 has addresses, 00 to 0N where N is arbitrary number. The write operation and the read operation are separately carried out in the increasing order of address. After the address ON is processed, address 00 is processed. Signals used on the write side of the elastic store memory are a clock 1, input data (write data), a write inhibit signal and a write reset signal. When the write reset signal produced and output by a write control circuit (not shown) is applied to the elastic store memory, the write address is set to be address 00. Signals used on the read side of the elastic memory are a clock 2, output data (read data), a read inhibit signal, a read reset signal and a phase comparison signal (hereinafter simply referred to as a PCO signal). The read reset signal is generated and output by a read control circuit (not shown). When the read reset signal is applied to the elastic store memory, the read address is set to address 00.
The elastic store memory recognizes that readout data is correct during the time when data is successively read out from a storage area specified by an address to which the writing of input data is already completed. When the bit rate of the read operation is greater than that of the write operation, there is a possibility that data related to an address for which the writing of new (next) input data has not yet been carried out is read out from a storage area specified by the above address. In other words, the same data is twice read out from the same storage area. On the other hand, when the bit rate of the read operation is less than that of the write operation, there is a possibility that before data is read out from a storage area, new input data is written into the above storage area. In this case, the above data which has not yet been read out is lost. The above-mentioned re-reading of data and lack of data is defined as a slip of data or data slip.
A phase comparator built in the elastic store memory compares the phase of the write reset signal and the phase of the read reset signal and determines whether or not the phase difference is small so that there is a possibility that the slip of data occurs. When the determination result is affirmative, the elastic store memory generates the PCO signal.
FIG. 3 is a waveform diagram illustrating how to generate the PCO signal. In FIG. 3, each of the clock signals 1 and 2 has an identical bit rate for the sake of simplicity. With respect to the write reset signal, (n-1) bits of the read reset signal before the write reset signal and (n+1) bits thereof after the same form an alarm area. If the read reset signal appears within the alarm area, the PCO signal (also called PCO alarm) is generated. The numeral n is set in the phase comparator provided in the elastic store memory. For example, n=2, 4, 8 or 16. For n=2, one bit of the read reset signal before the write reset signal and three bits thereof after the same form the alarm area.
The PCO signal is sent to a destination terminal together with readout data. The destination terminal can acknowledge the occurrence of the slip of data from the PCO signal. However, the destination terminal cannot understand the cause of the occurrence of data slip from the PCO signal. That is, the destination terminal cannot understand, from the PCO signal, whether the occurrence of data slip arises from the re-reading of data or the lack of data.